IC-16 — Modular 16-bit computer: one-size PCBs, keyed ISA-style slots, CPU-agnostic bus, retro heart modern lungs.
- Python 100%
| Filename | Latest commit message | Latest commit date |
|---|---|---|
| archive | ||
| easyeda | ||
| .gitignore | ||
| gen_b00_pico_visual.py | ||
| gen_batch1_boards.py | ||
| gen_no_offsets.py | ||
| gen_transfer.py | ||
| IC-16_Launch_Batches.md | ||
| IC-16_Modular_Computer_Spec_v0.1.md | ||
| IC16_19_no_offsets.png | ||
| IC16_20_batch1_boards.png | ||
| IC16_23_transfer.png | ||
| IC16_24_template.png | ||
| IC16_27_b00_pico_topdown.png | ||
| README.md | ||
IC-16 — Modular 16-Bit Computer System
Retro heart, modern lungs. Simple, fun, collectible PCB modules that plug together to make interesting computers.
- One PCB size only: 90 x 96mm, PC/104 mounting holes
- ISA-style slots on a dumb passive backplane (headers, not edge connectors)
- CPU-agnostic: 65C02 / Z80 / 6809 / homebrew TTL all speak one common bus
- Keyed so it can't plug backwards: PIN1 square + EAR hole + asymmetric L/R assignment + shrouded backplane box (v0.4 H1d-NK SIDES, no offsets)
- Dual power rails: skinny 2.54mm logic 5V + fat 3.96mm HP rail (S100-style raw)
- Modern first-class: sensors, ESP32 WiFi, Pico, Arduino, Pi — same footprint
Status
v0.4 DRAFT — aligned TOP32+BL15+BR15+edge power locked, EasyEDA template opens.
See IC-16_Modular_Computer_Spec_v0.1.md
(filename kept stable so graphic links don't break; header inside says v0.4).
Board workflow (one EasyEDA project per board)
Each board is its own EasyEDA Pro project (.eprj2) so a single board file
can be shared for help without exposing the whole system.
- Template (frozen master):
/home/merlin/Documents/EasyEDA-Pro/projects/IC16-template.eprj2— 90x96 base board: TOP 1-32 + BL 33-47 + BR 48-62 + edge PWR + M3/EAR + test points + PWR LED pads + keepout/bus-zone frames. Do NOT edit except to fix the template itself. - New board: open the template in EasyEDA Pro → File > Save As >
B-XX-name(own project) → design → the generator scripts stay in-repo (easyeda/) and are only re-run to fix/regenerate the template. - Preview proof:
IC16_24_template.pngis parsed back out of the built.eprj2and must match the lockedIC16_19_no_offsets.pnglayout.
Contents
| File | What |
|---|---|
IC-16_Modular_Computer_Spec_v0.1.md |
Full system ideas doc (vision, research, bus, power, roadmap) |
IC-16_Launch_Batches.md |
Batch 1 enablers + Batch 2 computer kits |
IC16_19_no_offsets.png |
LOCKED v0.4 layout: aligned TOP32+BL/BR+PWR, no offsets |
IC16_20_batch1_boards.png |
Batch 1 board top-downs |
IC16_23_transfer.png |
B-13T passive transfer (vertical DOWN, angle OUT) |
IC16_24_template.png |
Template proof, parsed back from the built .eprj2 |
IC16_27_b00_pico_topdown.png |
B-00 Proto Pico sniffer v0.3 draft (verified footprint, supersedes Nano/Pi-Zero drafts in archive/) |
easyeda/gen_template.py |
Builds IC16-template.eprj2 from the bundled example |
easyeda/gen_template_preview.py |
Renders IC16_24_template.png from the built .eprj2 |
gen_no_offsets.py, gen_batch1_boards.py, gen_transfer.py |
Scripts for the locked graphics above |
archive/ |
Superseded explorations, old graphics, KiCad v0.1 offset template |
Freedom rule (4 mandatory, rest wild)
- 90x96 + PIN1/EAR/asymmetric/shroud key + pin-1 right
- 500mA / 1x HC load max, 5V-only on logic bus
- GND star, no +/-12V/mains on bus
- Power LED + B-number + L/H mark on silkscreen
Analog / FPGA / valves / MIDI / drone / garden — if it fits and doesn't brown out the backplane, it's legal. Especially if it's weird.
Roadmap
- Tier 0 starter: B-01 backplane, B-02 clock, B-03 CPU, B-04 memory, B-05 blinkenlights, B-06 serial
- Tier 1 fun: Pico VGA, PS/2, YM2149 sound, SD+RTC, proto cards
- Tier 2 halo: TTL CPU rebuild, Pico debugger, sidecar link, power meter
- Tier M modern: sensor hub, ESP32 WiFi, Pico bridge, Pi terminal, Arduino I/O
License (proposed)
Open hardware — CC-BY-SA (or CERN-OHL-S) for pinout, EasyEDA template, backplane gerbers. Commercial clones allowed. Community cards get official B-numbers in the registry.